In a growing trend, semiconductor manufacturers have increasingly adopted three-dimensional (3D) interconnects and packaging for semiconductor devices. Three-dimensional interconnects give advantages such as size reduction, reduced interconnect length and integration of devices with different functionality within a respective package.
One of the various ways of implementing 3D interconnects involves using so-called “through-hole via” technology. The location of a through-hole via can be located either within a semiconductor chip, or “die,” or outside the die (i.e., along a so-called “saw street” guide).
However, current through-hole via technology poses several limitations. A via located within a semiconductor chip restricts the freedom of having additional circuitry within the chip. As can be appreciated, a respective location of a through-hole via forecloses the placement of circuitry at that location. As a result, the functionality of the chip, and therefore, a device making use of the chip, is limited.
A via located outside the semiconductor chip (i.e., along the saw street guide) necessitates a wider saw street to accommodate the creation of a through-hole. As a result, yields (i.e., chips per wafer) are reduced.